A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation

In this paper the architecture is described for a 32 bit, 15M FLOP floating point programmable signal processor that has been designed specifically for gate array implementation. After a brief discussion of the overall system a more indepth review of the 6 chips that make up the processor will be given. The 6 chips are: Microprogrammed Sequencer Unit, Address Computation Units Floating Point Execution Unit: Floating Point Multiplier, Floating Point Arithmetic Unit, Multiport Memory Unit, Divide/Square Root Unit.