Experiences with the Sparse Matrix-Vector Multiplication on a Many-core Processor

Author

Pichel, Juan C. ; Rivera, Francisco F.

Author_Institution

Centro de Investig. en Tecnoloxias da Informacion (CITIUS), Univ. de Santiago de Compostela, Santiago de Compostela, Spain

fYear

2012

fDate

21-25 May 2012

Firstpage

7

Lastpage

15

Abstract

Industry is moving towards many-core processors, which are expected to consist of tens or even hundreds of cores. One of these future processors is the 48-core experimental processor Single-Chip Cloud Computer (SCC). The SCC was created by Intel Labs as a platform for many-core research. The characteristics of this system turns it into a big challenge for researchers in order to extract performance from such complex architecture. In this work we study and explore the behavior of an irregular application such as the Sparse Matrix-Vector multiplication (SpMV) on the SCC processor. An evaluation in terms of performance and power efficiency is provided. Our experiments give some key insights that can serve as guidelines for the understanding and optimization of the SpMV kernel on this architecture. Furthermore, a comparison of the SCC processor with several leading multicore processors and GPUs is performed.

Keywords

cloud computing; graphics processing units; matrix multiplication; multiprocessing systems; 48-core experimental processor; GPU; Intel Labs; SCC; SpMV; complex architecture; many-core processor; multicore processors; single-chip cloud computer; sparse matrix-vector multiplication; Artificial neural networks; Clocks; Kernel; Mesh networks; Multicore processing; Sparse matrices; Tiles; many-core; performance; power efficiency; sparse matrix;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International

Conference_Location

Shanghai

Print_ISBN

978-1-4673-0974-5

Type

conf

DOI

10.1109/IPDPSW.2012.17

Filename

6270623