Low Power and High Speed Sample-and-Hold Circuit

This paper describes the improved sample- and-hold architecture as a front-end block of low power and high speed pipelined analog to digital converter. The circuit consists of bottom-plate sampling with differential architecture of OTA (operational transconductance amplifier). The sample-and-hold circuit has been laid out in 0.18 mum CMOS technology and simulated using MOSIS CMOS BSIM3v3.1 SPICE parameters. The measurement result shows that the SFDR of 64.5 dB is achieved up to the sampling frequency of 100MS/s for input signal amplitude of 1.2 Vpp.The sample-and-hold circuit consumes 6.5 mW from a 1.8 volt supply.