• DocumentCode
    2996685
  • Title

    A VLSI implementation of an FFT/NTT computational unit

  • Author

    Bayoumi, M.A. ; Jullien, G.A. ; Miller, W.C.

  • Author_Institution
    University of Windsor, Ontario, Canada
  • Volume
    10
  • fYear
    1985
  • fDate
    31138
  • Firstpage
    192
  • Lastpage
    195
  • Abstract
    The coupling of Residue Number System (RNS) with the recent advances in VLSI technology leads to an efficient implementation of many digital signal processing algorithms. This paper discusses modularity in implementing RNS systems, as modularity is considered an important criterion for VLSI design. An NTT/FFT computational unit is implemented using two multi-look-up table modules as building block units. The layout can be optimized using a look-up table layout procedure which supports the custom design approach. The modularity has been achieved on both functional and layout levels where the interconnection area is minimum.
  • Keywords
    Arithmetic; Concurrent computing; Design optimization; Digital signal processing; Digital signal processing chips; Dynamic range; Hardware; Medical services; Signal processing algorithms; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
  • Type

    conf

  • DOI
    10.1109/ICASSP.1985.1168491
  • Filename
    1168491