• DocumentCode
    2996702
  • Title

    Task Scheduling in Large-scale Distributed Systems Utilizing Partial Reconfigurable Processing Elements

  • Author

    Nadeem, M. Faisal ; Ashraf, Imran ; Ostadzadeh, S. Arash ; Wong, Stephan ; Bertels, Koen

  • Author_Institution
    Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
  • fYear
    2012
  • fDate
    21-25 May 2012
  • Firstpage
    79
  • Lastpage
    90
  • Abstract
    Recent progress in processing speeds, network bandwidths, and middleware technologies have contributed towards novel computing platforms, ranging from large-scale computing clusters to globally distributed systems. Consequently, most current computing systems possess different types of heterogeneous processing resources. Entering into the peta-scale computing era and beyond, reconfigurable processing elements such as Field Programmable Gate Arrays (FPGAs), as well as forthcoming integrated hybrid computing cores, will play a leading role in the design of future distributed systems. Therefore, it is important to develop simulation tools to measure the performance of reconfigurable processors in the current and future distributed systems. In this paper, we propose the design of a simulation framework to investigate the performance of reconfigurable processors in distributed systems. The framework incorporates the partial reconfigurable functionality to the reconfigurable nodes. Depending on the available reconfigurable area, each node is able to execute more than one task simultaneously. Furthermore as a case study, we present a simple task scheduling algorithm to verify the functionality of the simulation framework. The proposed algorithm supports the scheduling of tasks on partially reconfigurable nodes. The simulation results are based on various experiments and they provide a comparison between full (one node-one task mapping) and partial (one node-multiple tasks mapping) configuration of the nodes, for the same set of parameters in each simulation run. Results suggest that the average wasted area per task is less as compared to the full configuration, verifying the functionality of the simulation framework.
  • Keywords
    distributed processing; field programmable gate arrays; processor scheduling; reconfigurable architectures; FPGA; distributed systems; field programmable gate arrays; large scale distributed systems; middleware technologies; network bandwidths; one node multiple tasks mapping; one node one task mapping; partial reconfigurable functionality; partial reconfigurable processing elements; petascale computing; processing speeds; task scheduling; Computational modeling; Dynamic scheduling; Field programmable gate arrays; Processor scheduling; Program processors; Resource management; Distributed systems; Partial reconfiguration; Reconfigurable resources; Resource management; Simulation framework;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4673-0974-5
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2012.6
  • Filename
    6270629