DocumentCode
2996761
Title
High resolution digital filter chip
Author
Aliphas, Ainnon ; Ganong, William F., III ; Stonestrom, Peter ; Perkins, Dan
Author_Institution
Kurzweil Applied Intelligence, Waltham, MA
Volume
10
fYear
1985
fDate
31138
Firstpage
224
Lastpage
227
Abstract
A general purpose, programmable digital filter chip consisting of eight second order (2 poles & 2 zeros) sections was implemented in 4µ NMOS technology. This device uses 24 bit coefficients and data and 48 bits of internal accumulation. These features make this device better than existing 16 bit DSP chips in applications where quantization noise and digital filter stability are of critical importance. A bit serial architecture plus internal multiplexing integrates these eight second order sections in one 24 pin package. This component, named the KSC2408, can be configured (programmed) to be used in different modes and architectures. It is especially suited for digital filterbanks, since it has on-chip and across-chip multiplexing and output control signals. The KSC2408 also features on-chip rectification and output decimation.
Keywords
Clocks; Digital filters; Digital signal processing chips; Filtering; MOS devices; Poles and zeros; Quantization; Sampling methods; Silicon; Stability;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
Type
conf
DOI
10.1109/ICASSP.1985.1168495
Filename
1168495
Link To Document