Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Common features for comparing AES implementations are the latency and throughput of the module as well as its resource requirements. This work evaluates the robustness against punctual errors in the FPGA caused by SEUs or other effects for a variety of AES implementations in order to provide a possible additional feature differentiating various architectures. The AES implementations included in this work span from a speed of more than one Mcycle for one encryption to 16 cycles per encryption. A fault injection flow is executed on the different implementations in order to determine their robustness against these punctual errors.