Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation

As the complementary metal oxide semiconductor (CMOS) scaling become harder, researchers have been trying to improve field programmable gate array (FPGA) performance by utilizing nonvolatile memory devices. This paper reports on a novel FPGA architecture where nonvolatile memory devices are used as nonvolatile reconfigurable switches (NRSs). It has found that resistive change memory (RCM) can be utilized as idealistic NRSs. To evaluate future performance of FPGA, we established evaluation method of interconnect circuit from international technology roadmap for semiconductor (ITRS) forecast. From FPGA scale evaluation, we show that there are two important design factor which affects overall FPGA performance, nonvolatile memory device characteristics and logic block cluster size. In terms of nonvolatile memory device characteristics, we have shown that the memory device whose resistivity of low resistance state (LRS) is around 10 kW gives superior performance by analysis of area and delay tradeoff. In terms of cluster size, larger cluster size is better for NRS-based FPGA since it can utilize small local programmable interconnect circuit composed of nonvolatile memory devices. From quantitative evaluation, area, delay and power of NRS-based FPGA can be improved by 25%, 24%, 29% compared to CMOS-based FPGA for 21 nm technology.