Title :
Destage algorithms for disk arrays with non-volatile caches
Author :
Varma, Anujan ; Jacobson, Quinn
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
In a disk array with a nonvolatile write cache, destages from the cache to the disk are performed in the background asynchronously while read requests from the host system are serviced in the foreground. We study a number of algorithms for scheduling destages in a RAID-5 system. We introduce a new scheduling algorithm, called linear threshold scheduling, that adaptively varies the rate of destages to disks based on the instantaneous occupancy of the write cache. The performance of the algorithm is compared with that of a number of alternative scheduling approaches such as least-cost scheduling and high/low mark. The algorithms are evaluated in terms of their effectiveness in making destages transparent to the servicing of read requests from the host, disk utilization, and their ability to tolerate bursts in the workload without causing an overflow of the write cache. Our results show that linear threshold scheduling provides the best read performance of all the algorithms compared, while still maintaining a high degree of burst tolerance. An approximate implementation of the linear-threshold scheduling algorithm is also described. The approximate algorithm can be implemented with much lower overhead, yet its performance is virtually identical to that of the ideal algorithm.
Keywords :
cache storage; processor scheduling; redundancy; scheduling; software performance evaluation; storage management; RAID-5 system; algorithm performance; destage algorithms; destage scheduling; disk arrays; disk utilization; high/low mark; instantaneous write cache occupancy; least-cost scheduling; linear threshold scheduling; nonvolatile write cache; read performance; read request servicing; read requests; scheduling algorithm; transparent destages; workload burst tolerance; Availability; Concurrent computing; Disk drives; Jacobian matrices; Logic arrays; Maintenance; Parallel processing; Permission; Protection; Scheduling algorithm;
Conference_Titel :
Computer Architecture, 1995. Proceedings., 22nd Annual International Symposium on
Conference_Location :
Santa Margherita Ligure, Italy
Print_ISBN :
0-89791-698-0