Title :
Design and realization of a new chaotic neural encryption/decryption network
Author :
Su, Scott ; Lin, Alvin ; Yen, Jui-Cheng
Author_Institution :
Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miaoli, China
Abstract :
A new chaotic neural network and its VLSI architecture for digital signal encryption and decryption are proposed in the paper. According to a binary sequence generated from a chaotic system, the biases and weights of neurons are set. The chaotic neural network can be used to encrypt digital signals. The network´s features are as follows: (1) high security; (2) no distortion; and (3) suitable for system integration. The MATLAB simulation results are also included for demonstration. In order to implement the system, its VLSI architecture with low hardware complexity and high computing speed is also designed. Its FPGA realization result indicates that the proposed design works correctly and its encryption speed achieves 40 Mbps. It indicates that the integration of the proposed system and MPEG2 for TV distribution, communication, and storage is practicable
Keywords :
VLSI; binary sequences; chaos; cryptography; data compression; digital signal processing chips; field programmable gate arrays; neural chips; video coding; FPGA realization; MATLAB simulation; MPEG2; TV distribution; VLSI architecture; biases; binary sequence; chaotic neural encryption/decryption network; digital signal decryption; digital signal encryption; distortion-free operation; high computing speed; high security; low hardware complexity; system integration suitability; weights; Binary sequences; Chaos; Chaotic communication; Computational modeling; Computer architecture; Cryptography; MATLAB; Neural networks; Neurons; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913503
