Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices

Singular value decomposition (SVD) allows the factorization of real or complex matrices providing quantitative information with fewer dimensions along which data points exhibit more variation. These days SVD computation is being used in numerous applications, and because of its importance, different approaches for SVD hardware computation have been proposed, however, their application is limited by the inherent SVD calculation complexity making it possible to analyze up to 8 × 8 matrices until now, complying certain constrains like symmetry. This paper presents a generic and novel FPGA-based hardware architecture for SVD computation on large m × n matrices utilizing Hestenes approach and one-side Jacobi rotations. Four different study cases (2 × 2, 8 × 7, 16 × 32, and 32 × 127 matrices) validate the performance of the FPGA-based computation unit reaching a maximum estimation error of 3.3718% in the SVD estimation of a large matrix.