Vector multiprocessors with arbitrated memory access

The high latency of memory accesses is one of the factors that contributes to reduce the performance of current vector supercomputers. The conflicts that can occur in the memory modules plus the collisions in the interconnection network in case of multiprocessors make the execution time of applications increase significantly. In this work we propose a memory access method for vector uniprocessors and multiprocessors that allows to perform stream accesses with the smallest possible latency in the majority of the cases. The basic idea is to arbitrate the memory access by defining the order in which the memory modules are visited. The stream elements are requested out of order. In addition, the access method also reduces the cost of the interconnection network.