FPGA Bootstrapping on PCIe Using Partial Reconfiguration

For many FPGA-based computing systems, a dedicated FPGA or interface chip is included to provide I/O functionality. As commercial FPGA sincrease in size, they are becoming large enough to include both theI/O interface and the reconfigurable logic. It is non-trivial, however, to provide a consistent, uninterrupted I/O interface on a single FPGA that supports reconfiguration. This paper presents an FPGA-based PCIe computing system that uses bootstrapping to configure FPGA logic at run-time. A static FPGA circuit is created to provide the PCIe interface when the system is powered-up. At run-time, computational circuits are configured onto the device as partially reconfigured modules through the static PCIe interface. Several computing circuit examples from the ERC Bench benchmarking suite were used to demonstrate this technique.