Power estimation techniques for integrated circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: (1) the use of simplified delay models, and (2) modeling long-term behavior of logic signals with probabilities. The array of available techniques differ in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the different assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.