Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures

Triple modular redundancy (TMR) is a common method to implement fault-tolerant circuits. Traditionally, TMR is realized by triplication of components. In order to reduce the area overhead of TMR another approach was proposed on coarse grained reconfigurable architectures (CGRAs). In that approach spare functional units (FUs) are used for redundant computation of results. However, it was not shown that this approach is workable for any application. In this work we close that gap. We mapped several multipoint fast Fourier transform on a CGRA of different array sizes and analyzed the ratio of spare FUs to used FUs. If the number of spare FUs is not sufficient to find a fault-tolerant application mapping, we propose to use run-time reconfiguration to extend the number of spare FUs in the time domain. We compared this strategy with the traditional approach in terms of area and throughput. The comparing results show that run-time reconfiguration can be a suitable method for decreasing the area overhead of TMR, however at the expense of lower throughput.