Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure

Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even with sophisticated tools and improvements in high-level language to gates approaches, an engineer can expend significant effort simply implementing the design. Often, when the design is evaluated on the FPGA, the performance may not be what was expected. As a result, an engineer may go back and augment the design to include performance monitors to help identify the bottlenecks in the system or to aid in the debugging of the design. This work aims to alleviate this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend/insert performance monitors directly into the HDL, and retrieve the monitored data with minimal invasion to the design. This paper reports on the functionality of the tools and the integration of the hardware cores into existing designs.