DocumentCode
2997398
Title
On testable multipliers for fixed-width data path architectures
Author
Mukherjee, N. ; Rajski, J. ; Tyszer, J.
Author_Institution
MACS Lab., McGill Univ., Montreal, Que., Canada
fYear
1995
fDate
5-9 Nov. 1995
Firstpage
541
Lastpage
547
Abstract
The usage of multipliers in the increasingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output responses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to improve the overall testability of data paths. The methodology takes into account the truncated least significant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal performance degradation and area overhead.
Keywords
computer architecture; design for testability; digital arithmetic; logic CAD; logic circuits; logic testing; Arithmetic Built-in Self Test; area overhead; data path architectures; fault observability; fixed-width; least significant bits; minimal performance degradation; testability; testable multipliers; Arithmetic; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Degradation; Design for testability; Graphics; Laboratories; Observability;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1995.480169
Filename
480169
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