Title :
An improved interlevel dielectric process for submicron double-level metal products
Author :
Pennington, Scott L. ; Luce, Stephen E. ; Hallock, Dale P.
Author_Institution :
IBM, Essex Junction, VT, USA
Abstract :
An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time
Keywords :
VLSI; chemical vapour deposition; etching; metallisation; Ar sputtering; CVD film deposition; SiO2 dielectric layers; VLSI; anisotropic oxide etching; deposition process; etching; interlevel dielectric process; low temperature dielectric; multichamber tool; multilevel interconnection; multitool process; plasma enhanced CVD TEOS oxide; process queuing time; reduces wafer handling; single cassette-to-cassette operation; submicron double-level metal products; thermal CVD TEOS oxide films; void-free interlevel dielectric; Anisotropic magnetoresistance; Argon; Dielectrics; Metal products; Plasma applications; Plasma properties; Plasma temperature; Plasma transport processes; Sputter etching; Sputtering;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1989.77994
