EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture

In this study, we developed and implemented a placement and routing algorithm for a new switch-block-free fine-grain reconfigurable device, called MPLD, as an evaluation environment of MPLD´s ability to realize sequential circuits. An MPLD consists of an array of multiple-output LUTs (MLUTs), which work as logic elements and/or routing elements, and has no switch blocks for routing, unlike FPGAs. Thus, when the logic cells of a circuit are placed on an MPLD, MLUTs need to be reserved for routing around the placed logic cells. Our simulated annealing-based placement algorithm for MPLDs avoids overcrowding logic cells and reserves routing space, by considering (1) detailed estimated wire congestion and (2) distance between logic cells, in its cost function. In experiments, we confirmed that sequential circuits were successfully placed and routed on MPLDs in our evaluation environment.