Title :
Evaluation of a novel passivation process for submicron CMOS SRAMs using PETEOS in combination with other PECVD films
Author :
Gootzen, W. ; Bellersen, M. ; de Bruin, L. ; Rao, G. ; Rutten, G. ; Yen, D.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7-μm and 0.5-μm CMOS SRAM processes is proposed
Keywords :
CMOS integrated circuits; VLSI; chemical vapour deposition; integrated circuit technology; integrated memory circuits; metallisation; passivation; random-access storage; reliability; 0.5 micron; 0.7 micron; CMOS SRAMs; PECVD films; PECVD-TEOS; VLSI; electrical behavior; failure mechanisms; final passivation layer; multilevel interconnection; passivation process; passivation schemes; reliability; submicron; CMOS process; Delay effects; Dielectric materials; Failure analysis; High-K gate dielectrics; Laboratories; Moisture; Packaging; Passivation; Random access memory;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1989.77995
