Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application

Dynamic Partial Reconfiguration (DPR) allows modification of certain parts of an FPGA while the rest of the device continues to operate and remains unaffected by the partial reprogramming. DPR for FPGA-based designs is an increasingly important feature in many systems that must adapt quickly to changing run-time requirements. Particularly in aerospace applications, the reuse and on-line reprogramming is a key aspect as the access to the system to re-design the hardware it is not a trivial task. We propose an autonomous reconfigurable digital signal processing architecture tailored for the utilization of FPGA resources efficiently. This paper deals with an efficient way of DSP computing by means of DPR applied to a hardware module and discusses execution time, flexibility and area savings. Reconfiguration on a co-processor is introduced to perform mathematical operations separately but using the same resources. Some overhead in timing is justified by the reduction in area obtained. Software application and hardware module performances are analyzed in terms of area and time to compare the benefits of the approach.