On Dynamic Run-time Processor Pipeline Reconfiguration

Adaptation of hardware in relation to the requirements of a specific application is well known and investigated in the domain of Field Programmable Gate Arrays (FPGA) based reconfigurable system architectures. In these system approaches, a number of predefined blocks, mainly accelerators for processors, are loaded from an external storage and are transferred to the FPGA configuration memory in order to manipulate the on-chip functionality. A novel approach is to adapt the micro architecture of a processor in order to achieve a temporal application-specific behavior. In combination with the well known techniques of dynamic reconfiguration of a FPGA, novel degrees of freedom are available for an energy efficient run-time dynamic system approach. This paper presents one adaptation mechanism, in which the pipeline depth is adapted according to the control flow and data flow of an application. The concept and also the realization are described and evaluated in terms of efficiency with some benchmarks.