Title :
Low Power Arithmetic Circuits in Feedthrough Dynamic CMOS Logic
Author :
Navarro-Botello, Victor ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid ; Dyer, Mike
Author_Institution :
Univ. of Las Palmas de Gran Canaria, Las Palmas
Abstract :
This paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) [1] concept. Low power FTL arithmetic circuits provide for smaller propagation time delay (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.
Keywords :
CMOS logic circuits; adders; logic design; low-power electronics; CMOS logic circuits; feedthrough logic arithmetic circuits; propagation time delay; ripply carry adder design; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Delay effects; Energy consumption; Logic circuits; Logic design; Pulse inverters; Telecommunication standards;
Conference_Titel :
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location :
San Juan
Print_ISBN :
1-4244-0172-0
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2006.382161
