Title :
Performance test of Viterbi decoder for wideband CDMA system
Author :
Park, Jang-hyun ; Rho, Yea-Chul
Author_Institution :
Signal Process. Sect., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
Abstract :
This paper describes the design, the implementation, and the performance test of the Serial Viterbi decoder (SVD) using VHDL and FPGAs. The decoding scheme assumes the transmitted symbols were coded with a K=9, 32 Kbps, and rate 1/2 convolutional encoder with generator function g0=(753)8 and g1=(561)8 as defined in the JTC TAG-7 W-CDMA PCS standard. The SVD is designed using VHDL and implemented using FPGAs. The main algorithm is implemented in two Altera FLEX81500 FPGAs. The performance test results with 3DB Gaussian noise show that the SVD works well
Keywords :
Gaussian noise; Viterbi decoding; broadband networks; code division multiple access; field programmable gate arrays; hardware description languages; logic CAD; telecommunication computing; telecommunication standards; testing; 32 kbit/s; Altera FLEX81500; CDMA PCS standard; FPGA; Gaussian noise; Serial Viterbi decoder; VHDL; Viterbi decoder performance testing; convolutional encoder; decoding scheme; generator function; symbols; wideband CDMA system; Code standards; Convolutional codes; Decoding; Field programmable gate arrays; Gaussian noise; Multiaccess communication; Personal communication networks; System testing; Viterbi algorithm; Wideband;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600052
