Using dynamic partial reconfiguration approach to read sensor with different bus protocol

The aim of this paper is to present an efficient design approach called partial reconfiguration to design a sensors reading system for road safety. The soaring price of energy has lead designers to think of new approach to reduce the FPGA device utilization therefore the power consumption. The partial reconfiguration flow can exponentially increase the functionality of a single FPGA allowing a system to be implemented with fewer and smaller devices than otherwise require. The partial reconfiguration (PR) is a feature that allows multiple design modules to time share physical resources. The partial reconfiguration module (PRM) can be swapped on the fly while the based design continues to operate. A Virtex 5 board an ICAP (internal configuration access port), ISE (integrated software environment) 9.2 Service Pack 4 with the partial reconfiguration layout PR7, XPS (Xilinx platform studio) 9.2 Service Pack 2, PlanAhead 10.1.6 and Chipscope 9.2 Service Pack 4 will be used to demonstrate how useful that flow can be to read a certain number of sensors at different times for different applications.