DocumentCode
2998501
Title
Highly scalable sub-50nm vertical double gate trench DRAM cell
Author
Schloesser, T. ; Manger, D. ; Weis, R. ; Slesazeck, S. ; Lau, F. ; Tegen, S. ; Sesterhenn, M. ; Muemmler, K. ; Nuetzel, J. ; Temmler, D. ; Kowalski, B. ; Scheler, U. ; Stavrev, M. ; Koehler, D.
Author_Institution
Memory Dev. Center, Infineon Technol., Dresden, Germany
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
57
Lastpage
60
Abstract
Results of a highly scalable 8F2 DRAM cell are presented. For the first time the fabrication of a fully depicted vertical transistor DRAM is demonstrated. Based on extensive process and device simulations, the scalability of the proposed cell beyond the 50nm DRAM node is highlighted.
Keywords
DRAM chips; nanoelectronics; 50 nm; 8F2 DRAM cell; device simulations; gate trench; vertical transistor; Capacitors; Doping profiles; Electrons; Fabrication; Implants; Random access memory; Scalability; Technological innovation; Transistors; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419064
Filename
1419064
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