Enhanced data retention of damascene-finFET DRAM with local channel implantation and <100> fin surface orientation engineering

Author

Lee, Chul ; Yoon, Jae-Man ; Lee, Choong-Ho ; Park, Jong Chul ; Kim, Tae Yong ; Kang, Hee Soo ; Sung, Suk Kang ; Cho, Eun Suk ; Cho, Hye Jin ; Ahn, Young Joon ; Park, Donggun ; Kim, Kinam ; Ryu, Byung-Il

Author_Institution

R & D Center, Samsung Electron., Yongin, South Korea

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

61

Lastpage

64

Abstract

80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).

Keywords

DRAM chips; field effect transistors; ion implantation; surface treatment; 512M DRAM; 80 nm; <100> fin surface orientation engineering; cell array transistor; channel directional wafer; contact resistance; damascene technology; damascene-finFET DRAM; data retention time; electron mobility; junction leakage; local channel implantation; local channel ion implantation; surface treatment; Contact resistance; Data engineering; Doping; Electron mobility; Etching; FinFETs; Ion implantation; Random access memory; Research and development; Surface treatment;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419065

Filename

1419065