Testing a Partial Reconfiguration based design for sensor reading

The aim of this paper is to present the methodology and tools used to debug a system comprising a HDL, microprocessor and Rocket I/O in a Partial Reconfiguration flow for sensor reading. The complexities of this system make it impossible to use a simple simulation tool such as Modelsim to assess the top level design functionality. The Bus Macros (BM) that interface between the static region and the reconfigurable region of the top level design make it impossible, as there is no simulation model for them. In general, 30% of the development time is taken by design and 70% by the test of the design functionalities. But many factors tend to increase testing time. The following are some of them: important signals are embedded deep in logic, design parts run at different speeds, so the computer screen cannot show all the data in different clock domains at the same time; the simulation time is too long; the design works in simulation but it does not work in hardware, and so on. This paper will present a practical case and the strategy used to debug it. The following software are used for these tests: ISE (Integrated Software Environment) 9.2 Service Pack 4 with the Partial Reconfiguration layout PR7, XPS (Xilinx Platform Studio) 9.2 Service Pack 2, PlanAhead 10.1.6, Chipscope 9.2 Service Pack 4 and two Virtex-5 boards.