Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: enhanced performance at reduced gate leakage

Author

Gusev, E.P. ; Cabral, C. ; Under, B.P. ; Kim, Y.H. ; Maitra, K. ; Carrier, Erin ; Nayfeh, H. ; Amos, R. ; Biery, G. ; Bojarczuk, N. ; Callegari, A. ; Carruthers, R. ; Cohen, S.A. ; Copel, M. ; Fang, S. ; Frank, M. ; Guha, S. ; Gribelyuk, M. ; Jamison, P.

Author_Institution

IBM Semicond. R&D Center, IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

79

Lastpage

82

Abstract

The key result in this work is that FUSI/HfSi_xO_y gate stacks offer both significant gate leakage reduction (due to high-κ) and drive current improvement at T_inv ∼ 2 nm (due to: (i) elimination of poly depletion effect, ∼ 0.5 nm, and (ii) the high mobility of HfSi_xO_y). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)∼ -0.4 V and Vt(NFET) ∼ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V_t stability) was found in the case of NiSi/ HfSi_xO_y compared to the same gate electrode with HfO₂ dielectric.

Keywords

dielectric materials; electron mobility; electron traps; field effect transistors; hafnium alloys; ion implantation; isolation technology; nickel compounds; stacking; FUSI alloying; HfSi_xO_y; NFET; NiSi-HfSiO; PFET; charge trapping; dielectrics; drive current improvement; fully silicided gates; gate electrode; gate leakage reduction; gate stacks; poly depletion effect; Alloying; Artificial intelligence; Gate leakage; High-K gate dielectrics; Jamming; Leakage current; Microelectronics; Research and development; Stability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419071

Filename

1419071