Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS

Author

Aimé, Delphine ; Froment, B. ; Cacho, F. ; Carron, V. ; Descombes, S. ; Morand, Y. ; Emonet, N. ; Wacquant, F. ; Farjot, T. ; Jullian, S. ; Laviron, C. ; Juhel, M. ; Pantel, R. ; Molins, R. ; Delille, D. ; Halimaoui, A. ; Bensahel, D. ; Souifi, A.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

87

Lastpage

90

Abstract

A wide workfunction (Φ_m) tuning range from 4.29eV to 4.99eV using total silicidation of doped polysilicon gate with nickel is presented. As, B and P but also N, Ge, Sb, In and co-implants, have been investigated to modulate the NiSi gate workfunction by dopant pile up effect at the silicide/dielectric interface. For the first time, defectivity data on dual gate oxide are presented, in correlation with the activation annealing impact and back end of line (BEOL) thermal stress effects as well as thorough TEM observations.

Keywords

CMOS integrated circuits; doping; interface structure; nickel compounds; silicon; thermal stresses; transmission electron microscopy; work function; 4.29 to 4.99 eV; CMOS; Ni; TEM observations; annealing impact; dopant pile up effect; dopant scanning; polysilicon gate; silicidation; silicide-dielectric interface; thermal stress effects; work function tuning; Annealing; Boron; CMOS technology; Capacitance-voltage characteristics; Capacitors; Fabrication; Nickel; Silicidation; Silicon; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419073

Filename

1419073