Performance and reliability driven clock scheduling of sequential logic circuits

Author

Takahashi, Atsushi ; Kajitani, Yoji

Author_Institution

Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan

fYear

1997

fDate

28-31 Jan 1997

Firstpage

37

Lastpage

42

Abstract

It is known that the clock-period in a sequential circuit can be shorter than the maximum signal delay between registers if the clock arrival time to each register is controlled. We propose an algorithm to find the minimum clock-period of a circuit whose signal propagation delays are given. Experimental results on LGSynth93 benchmarks show that this technique achieves as much as about 16% reduction of clock-period compared with the conventional maximum signal delay based methods. An application of this technique to improve the reliability of circuits is considered

Keywords

clocks; delays; directed graphs; logic CAD; scheduling; sequential circuits; LGSynth93 benchmarks; clock arrival time; clock scheduling; clock-period; directed graph; logic circuit reliability; maximum signal delay; registers; sequential logic circuit performance; signal propagation delays; Clocks; Delay effects; Polynomials; Propagation delay; Registers; Reliability engineering; Routing; Sequential circuits; Signal design; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

0-7803-3662-3

Type

conf

DOI

10.1109/ASPDAC.1997.600055

Filename

600055