Design of frame buffer for 1 THz energy efficient digital image processor based on HSLVDCI I/O standard in FPGA

This paper proposes design of frame buffer for a digital image processor. This design is implemented on Virtex-6 Field Programmable Gate Array (FPGA). In this work, three classes of High-Speed Low Voltage Digitally Controlled Impedance (HSLVDCI) are used to compare dynamic power requirements for the frame buffer. The experiment is performed at 1 GHz, 10 GHz, and 100 GHz and 1 THz device frequencies. The power utilization of the frame buffer is compared to find out the most energy efficient class of HSLVDCI. Dynamic power consists of clock power, logic power, signal power and I/O power. I/O power is higher than any other dynamic power, whereas logic power is the least used dynamic power. It is observed that the power requirements for clock, logic and signal are same for all the three I/O standards. There is an increase in I/O power with the increase in reference voltage of I/O standard. When frame buffer is operating at 1 GHz, the reduction in I/O power requirement of HSLVDCI_18 is 36.84% and of HSLVDCI_15 is 52.63% as compared to HSLVDCI_25. There is an improvement of 36.17% and 53.19% in I/O power when implemented with HSLVDCI_18 and HSLVDCI_15 respectively, as compared to HSLVDCI_25, at 10 GHz. When operating at 100 GHz, there is a reduction of 36.08%, 53.14% in I/O power of HSLVDCI_18 and HSLVDCI_15 respectively as compared to HSLVDCI_25. Also, the I/O power required by HSLVDCI_18 and HSLVDCI_15 is 36.09%, 53.14% lower respectively, than required in HSLVDCI_25, for the case of 1THz operating frequency.