Low power reconfigurable FIR filter based on window techniques for on chip network

Past literature analyzed FIR filter either for one or different order using either one or different window functions. In this brief, we have analyzed the performance of Reconfigurable Digital Low Pass FIR Filter System On Chip design for various filter orders 10 to 120 for different window techniques namely Rectangular, Hanning, Hamming, Bartlett and Kaiser Window Function, with sampling frequency 48 KHz and with cut off frequency 10.8 KHz. It is shown that filter design by using Kaiser window function and Spartan 6 family of FPGA is best because resource utilization are less and consequently the power consumption is minimum for this combination. Xilinx Spartan 6 family synthesis result of the designed filter using Kaiser Window Function shows 5-10% power reduction over other window function. On contrary to past literature, we have concluded the calculated parameters i.e. Power Consumption (Static and Dynamic), Delay, Resources Utilized by taking different window function as platform on the various FPGA families of Xilinx, so as to exploit best chosen family and window function according to application, specification as well as constraints. The coefficient of FIR filter is generated using MatLab FDA (Filter Design Analysis) tool box. Based on the coefficients, FIR filter is being programmed in VHDL, and synthesized and simulated on Xilinx design suite 14.1 ISE.