Title :
A Delay Model for SRAM-Based FPGA Interconnections
Author :
Yi, Wang ; Lingli, Wang ; Ruonan, Han ; Jiarong, Tong
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai
Abstract :
This paper proposes a delay model for SRAM-Based FPGA Interconnections. First, an equivalent resistance delay model is presented based on 50% timing delay for step input. The equivalent capacitance delay model is thereafter proposed for the ramp input The corresponding effective capacitance delay calculation method is also given. The experimental results show the efficiency and accuracy of the proposed delay model for the FPGA interconnections.
Keywords :
SRAM chips; delay circuits; field programmable gate arrays; integrated circuit interconnections; integrated circuit modelling; SRAM-based FPGA interconnections; effective capacitance delay calculation method; equivalent capacitance delay model; equivalent resistance delay model; timing delay; Capacitance; Delay effects; Delay estimation; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; MOSFETs; Resistors; Threshold voltage; Wire;
Conference_Titel :
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location :
San Juan
Print_ISBN :
1-4244-0172-0
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2006.382213
