A WSI oriented two dimensional systolic array for FFT

We consider a new architecture for a WSI (Wafer Scale Integration) oriented FFT processor. A two dimensional systolic array and a parallel FFT algorithm are proposed. The most significant problems are communications, reconfiguration and integrity. Considerations for those problems on WSI are presented. Our new algorithm enables computations of the FFT in parallel in any stage without multidimensional interconnections. Expected performance of the proposed architecture is also discussed.