Title :
A VLSI architecture design of VLC encoder for high data rate video/image coding
Author :
Chang, Hao-Chieh ; Chen, Liang-Gee ; Chang, Yung-Chi ; Huang, Sheng-Chieh
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An efficient architecture of variable length coding (VLC) is developed for recent multimedia applications, such as video and image compression. VLC plays a crucial part in these applications in that it provides a very effective coding gain. In this paper, we will describe an architecture design of VLC encoder. It can produce VLC codeword and amplitude, and pack them in order to achieve the constant word-length output. In addition, in this pipeline architecture, the VLC codeword and the amplitude can be processed in one clock cycle such that the input data rate of VLC encoder can reach as high as the sampling rate of video/image data. Therefore, it is very suitable for very high data rate video and image compression applications
Keywords :
VLSI; concatenated codes; data compression; digital signal processing chips; image coding; logic simulation; multimedia communication; parallel architectures; pipeline processing; programmable logic arrays; table lookup; variable length codes; video coding; PLA implementation; VLC encoder; VLSI architecture design; coding gain; concatenation; constant word-length output; critical path delay; data path; gate level design; high data rate video/image coding; image compression; logic synthesis; look-up table; multimedia applications; pipeline architecture; video compression; Clocks; Concatenated codes; Data compression; Image coding; Image sampling; MPEG 4 Standard; Pipelines; Very large scale integration; Video coding; Video compression;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780026
