DocumentCode :
2999150
Title :
A systolic vector quantization processor for real-time speech coding
Author :
Cappello, P. ; Davidson, G. ; Gersho, A. ; Koc, C. ; Somayazulu, V.
Author_Institution :
University of California, Santa Barbara, CA, USA
Volume :
11
fYear :
1986
fDate :
31503
Firstpage :
2143
Lastpage :
2146
Abstract :
The architecture and implementation of a novel VLSI bit-level systolic Vector Quantization processor is described. This architecture offers very high data throughput for real-time processing applications. Given a codebook of size 
and dimension 
, an input vector can be quantized every clock cycles, compared to O(kN) cycles for a Single-Instruction, Single-Data (SISD) machine. Any distortion measure which can be expressed as a Euclidean vector inner product can be computed with this array.
and dimension , an input vector can be quantized every clock cycles, compared to O(kN) cycles for a Single-Instruction, Single-Data (SISD) machine. Any distortion measure which can be expressed as a Euclidean vector inner product can be computed with this array.Keywords :
Clocks; Computer architecture; Distortion measurement; Mean square error methods; Pattern matching; Semiconductor device measurement; Speech coding; Throughput; Vector quantization; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
Type :
conf
DOI :
10.1109/ICASSP.1986.1168642
Filename :
1168642
Link To Document :
