Performance comparison of filter circuits based on two different current conveyor topologies

Author

Varshney, Garima ; Pandey, Narendra ; Pandey, Rashmi ; Bhattacharyya, A.

Author_Institution

Dept. of Electron. & Commun. Eng., Delhi Technol. Univ., New Delhi, India

fYear

2013

fDate

12-14 Dec. 2013

Firstpage

419

Lastpage

423

Abstract

This paper investigates the effect of two different second generation current conveyor (CCII) topologies on the behaviour of low pass, high pass and band pass filters. One of the current conveyor topology is based upon CMOS inverters and the other realization is based on translinear loop. 3-db bandwidth, Total Harmonic Distortion (THD) and output noise are used as comparison parameters. Simulation results show that THD of CMOS inverter´s based filters is lesser than that of the translinear loop based CCII filters. The former topology also enjoys better noise throughout its bandwidth against the latter one. All the simulations are done on PSPICE using typical BSIM3V3 0.35μm CMOS process parameters.

Keywords

CMOS integrated circuits; band-pass filters; current conveyors; harmonic distortion; high-pass filters; logic gates; low-pass filters; BSIM3V3 0.35μm CMOS process parameters; CCII topologies; CMOS inverters; PSPICE; THD; band pass filter; high pass filters; low pass filters; output noise; second generation current conveyor topologies; size 0.35 mum; total harmonic distortion; translinear loop; CMOS inverter; Second generation current conveyor; filters; transconductance mode; translinear loop;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Communication (ICSC), 2013 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-1605-4

Type

conf

DOI

10.1109/ICSPCom.2013.6719825

Filename

6719825