A RTL partitioning method with a fast min-cut improvement algorithm

Author

Kawaguchi, Kenichi ; Iwasaki, Chie ; Muraoka, Michiaki

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1997

fDate

28-31 Jan 1997

Firstpage

57

Lastpage

60

Abstract

A design flow with register transfer level (RTL) partitioning and an RTL partitioning algorithm for efficient logic synthesis and layout are described in this paper. By changing the parameter of the partitioning optimization dynamically, the algorithm improves the interconnection cost in a short CPU time. Experimental results on large circuits show that the algorithm partitioned circuits with a large number of RTL components in 1/10 to 1/100 of conventional partitioning times

Keywords

circuit layout CAD; circuit optimisation; computational complexity; logic CAD; logic partitioning; CPU time; RTL partitioning method; circuit layout; design flow; fast min-cut improvement algorithm; interconnection cost; logic synthesis; partitioning optimization parameter; partitioning time; register transfer level; Algorithm design and analysis; Central Processing Unit; Circuit synthesis; Hardware design languages; Integrated circuit interconnections; Iterative algorithms; Logic circuits; Logic design; Partitioning algorithms; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

0-7803-3662-3

Type

conf

DOI

10.1109/ASPDAC.1997.600058

Filename

600058