Title :
Modular design and hierarchical abstraction in Phideo
Author :
Lippens, P.E.R. ; Van Meerbergen, J.L. ; Verhaegh, W.F.J. ; van der Werf, A.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
The authors discuss a modular design approach in the context of high-level synthesis. A design is considered as a set of modules which are each synthesized separately. After each synthesis step an abstraction of a module is made which is used at the next hierarchical level. The modular design concept is discussed in the context of the Phideo compiler. It is shown that the same architecture and the same synthesis tools can be used at all levels
Keywords :
VLSI; circuit layout CAD; hardware description languages; high level synthesis; signal flow graphs; Phideo compiler; VLSI; bottom-up implementation strategy; complex time shapes; hierarchical abstraction; high-level synthesis; modular design approach; periodic operations; Arithmetic; Bandwidth; Design methodology; High level synthesis; Shape; Very large scale integration;
Conference_Titel :
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location :
Veldhoven
Print_ISBN :
0-7803-0996-0
DOI :
10.1109/VLSISP.1993.404487
