Title :
Design Techniques and Considerations for a 1.2V 10bit CMOS Pipeline ADC
Author :
Sun, Jia ; Meng, Hao ; Paasio, Ari
Author_Institution :
Electron. Lab., Univ. of Oulu, Oulu, Finland
fDate :
March 30 2011-April 1 2011
Abstract :
A 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33LSB respectively, while SNDR is 57.7dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; integrated circuit noise; operational amplifiers; CMOS pipeline ADC; capacitance optimization; comparator; noise analysis; operational amplifier; power consumption; size 130 nm; switches; voltage 1.2 V; word length 10 bit; CMOS integrated circuits; Capacitance; Logic gates; Noise; Operational amplifiers; Pipelines; Transistors; ADC; CMOS; capacitance optimization; comparator; noise analysis; operational amplifier; pipeline;
Conference_Titel :
Computer Modelling and Simulation (UKSim), 2011 UkSim 13th International Conference on
Conference_Location :
Cambridge
Print_ISBN :
978-1-61284-705-4
Electronic_ISBN :
978-0-7695-4376-5
DOI :
10.1109/UKSIM.2011.107
