Title :
A non-slicing floorplanning algorithm using corner block list topological representation
Author :
Hong, Xiunlong ; Dong, Sheqin ; Huang, Gang ; Yuchun Ma ; Cai, Yici ; Cheng, Chung-Kuan ; Gu, Jun
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
Corner Block List (CBL)-a new efficient topological representation for a non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a CBL, it takes only linear time to construct the floorplan. CBL defines the floorplan independent of the block size, so the structure is better suited to floorplan optimization with various size configurations of each block. Based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. Soft blocks, the aspect ratio of the chip and boundary constraints are taken into account in the simulated annealing process. The experimental results demonstrate the algorithm is quite promising
Keywords :
VLSI; circuit layout CAD; circuit optimisation; data structures; integrated circuit layout; network topology; simulated annealing; VLSI floorplan; boundary constraints; building block placement; chip aspect ratio; corner block list; floorplan optimization; linear time; mosaic floorplan; nonslicing floorplanning algorithm; simulated annealing technique; topological representation; Application software; Binary trees; Computer science; Simulated annealing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913650
