JHDL Implementation of a BIST Scheme for Testing the Look-Up Tables of SRAM Based FPGAs

Author

Niamat, M. ; Santhanam, S. ; Kim, J.

Author_Institution

Dept. of Eng. Technol., Toledo Univ., Toledo, OH

Volume

2

fYear

2006

fDate

6-9 Aug. 2006

Firstpage

327

Lastpage

331

Abstract

Built in self test for FPGAs has become an important area of research over the years. The current research focuses on the use of JHDL as an implementation tool for BIST. The research spans the design, simulation and JHDL implementation of a BIST scheme for testing the Look-Up Tables of a Xilinx SRAM based Spartan II FPGA. To the best of our knowledge, this is the first attempt by any researcher in using JHDL for implementing BIST on FPGAs.

Keywords

SRAM chips; built-in self test; field programmable gate arrays; integrated circuit design; integrated circuit testing; table lookup; BIST scheme; JHDL implementation; Xilinx SRAM based Spartan II FPGA; built-in-self test; integrated circuit design; integrated circuit testing; look-up tables; Automatic testing; Built-in self-test; Circuit testing; Design automation; Dynamic programming; Field programmable gate arrays; Hardware design languages; Integrated circuit interconnections; Java; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on

Conference_Location

San Juan

ISSN

1548-3746

Print_ISBN

1-4244-0172-0

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2006.382278

Filename

4267356