Title :
A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories
Author :
Ranica, R. ; Villaret, A. ; Fenouillet-Beranger, C. ; Malinge, P. ; Mazoyer, P. ; Masson, P. ; Delille, D. ; Charbuillet, C. ; Candelier, P. ; Skotnicki, T.
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85°C. Nondestructive reading is demonstrated at 25°C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.
Keywords :
DRAM chips; nanoelectronics; nondestructive readout; silicon-on-insulator; thin film circuits; 16 nm; 25 C; 75 nm; 85 C; capacitor-less DRAM cell; disturb margins; double gate architecture; eDRAM requirements; fully depleted SOI device; high density embedded memories; matrix integration; nondestructive reading; retention time; short gate length; thin film; CMOS technology; Capacitors; MOSFETs; Oxidation; Random access memory; Semiconductor thin films; Substrates; Thin film devices; Time measurement; Voltage;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419131
