Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Author

Shino, Tomoaki ; Higashi, Tomoki ; Kusunoki, Naoki ; Fujita, Katsuyuki ; Ohsawa, Takashi ; Aoki, Nobutoshi ; Tanimoto, Hiroyoshi ; Minami, Yoshihiro ; Yamada, Takashi ; Morikado, Mutsuo ; Nakajima, Hiroomi ; Inoh, Kazumi ; Hamamoto, Takeshi ; Nitayama, Ak

Author_Institution

SoC R&D Center, Toshiba Corp., Yokohama, Japan

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

281

Lastpage

284

Abstract

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

Keywords

CMOS logic circuits; embedded systems; semiconductor storage; silicon-on-insulator; 55 nm; FD operation; enlarged signal window; fully-depleted floating body cell; high-density embedded memory; logic process compatibility; negative substrate bias; standard salicide process; CMOS logic circuits; CMOS technology; Data mining; Integrated circuit technology; Logic devices; Microelectronics; Research and development; Semiconductor films; Signal processing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419132

Filename

1419132