Title :
A single-pass, in-situ planarization process utilizing TEOS for double-poly, double-metal CMOS technologies
Author :
Mehta, Sunil ; Sharma, Gian
Author_Institution :
Cypress Semicond., San Jose, CA, USA
Abstract :
A planarization technique utilizing in situ etching of TEOS-based CVD oxide is presented. The process includes TEOS/O2-based PECVD oxide, TEOS/O3-based LPCVD oxide, Ar+ sputter etching, and CF4-based reactive ion etching, all in a single pumpdown. This planarization process has been successfully used to fabricate advanced double-poly double-metal circuits on 0.8-μm CMOS technologies. E-test structures indicate low via resistance (0.15 Ω/via) and the absence of any metal opens or shorts. Custom-designed defect monitors show extremely low defect densities for both vias and metal. Comparison of die yields for the new in situ TEOS-etchback process and an SOG-etchback process indicates that much higher yields can be obtained by the use of the new process
Keywords :
CMOS integrated circuits; CVD coatings; integrated circuit technology; metallisation; sputter etching; 0.8 micron; Ar+ sputter etching; CMOS technologies; E-test structures; LPCVD oxide; PECVD oxide; TEOS-based CVD oxide; custom designed defect monitors; defect densities; die yields; double-poly double-metal circuits; in situ etching; in-situ planarization; reactive ion etching; tetrafluoromethane; via resistance; Argon; CMOS process; CMOS technology; Geometry; Magnetic films; Planarization; Plasma applications; Plasma temperature; Sputter etching; Surfaces;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1989.78009
