DocumentCode :
3000236
Title :
Finding clusters in VLSI circuits
Author :
Garbers, J. ; Promel, H.J. ; Steger, A.
fYear :
1990
fDate :
11-15 Nov. 1990
Firstpage :
520
Lastpage :
523
Abstract :
Circuit partitioning plays a fundamental role in hierarchical layout systems. Identifying the strongly connected subcircuits, the clusters, of the logic can significantly reduce the delay of the circuit and the total interconnection length. Finding such a cluster partition however, is NP-complete. The authors propose a fast heuristic algorithm based on a simple, local criterion. They are able to prove that for highly structured circuits the clusters found by this algorithm correspond with high probability to the ´natural´ clusters. An application to large scale real world circuits shows that by this method the number of nets cut is reduced by up to 46% compared to the standard mincut approach.<>
Keywords :
VLSI; circuit layout CAD; computational complexity; NP-complete; cluster partition; clusters; fast heuristic algorithm; hierarchical layout systems; Clustering algorithms; Delay; Heuristic algorithms; Integrated circuit interconnections; Iterative methods; Large-scale systems; Logic circuits; Mathematics; Partitioning algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
Type :
conf
DOI :
10.1109/ICCAD.1990.129970
Filename :
129970
Link To Document :
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