A practical algorithm for connectivity extraction for very large VLSI layouts

Moore´s law is alive and well. With designs entering the billion transistor era, there is an ever increasing demand on CAD tools to handle larger data sizes efficiently. One problem with processing large VLSI layouts is that the data to be processed is far too massive to fit into main memory. When dealing with data sets of sizes exceeding main memory, communication between the fast internal memory and the slow external memory is often the performance bottleneck and algorithms and data structures designed under the assumption of a single level of memory may not be meaningful. External memory algorithms try to optimize performance by taking into account disk accesses. One can certainly use the standard main memory algorithms for data that reside on disk but their performance is often considerably below the optimum because there is no control over how the operating system performs disk accesses. On demand thrashing can be high thus resulting in an increase in response time.