• DocumentCode
    3000626
  • Title

    Structural approach for performance driven ECC circuit synthesis

  • Author

    Su, Chauchin ; Chen, Kathy Y. ; Jou, Shyh-Jye

  • Author_Institution
    Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
  • fYear
    1997
  • fDate
    28-31 Jan 1997
  • Firstpage
    89
  • Lastpage
    94
  • Abstract
    ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization, and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits
  • Keywords
    error correction codes; logic CAD; ECC circuit synthesis; ECCGen; error control coding circuits; gate/pin assignment; literal minimization; logic synthesis; logic synthesizer; performance driven; Boolean functions; Circuit synthesis; Circuit testing; Error correction; Error correction codes; Explosions; Logic circuits; Minimization; Synthesizers; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    0-7803-3662-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1997.600065
  • Filename
    600065