DocumentCode
3000904
Title
Enumerating the min-cuts for applications to graph extraction under size constraints
Author
Azegami, Kengo R. ; Takahashi, Atsushi ; Kajitan, Y.
Author_Institution
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Volume
6
fYear
1999
fDate
36342
Firstpage
174
Abstract
Given an undirected hypergraph G0 with two vertices s and t specified, our problem is to extract a maximal subgraph under a constraint. It comprises two terms, the upper bound of the area and the cut separating the subgraph being an s-t minimum cut. If G0 is a model of a logic circuit, this is a faithful problem formulation in implementation of PPGA or MCM. Aiming to support such a design, we propose a representation of the s-t minimum cut of G0 in terms of a directed acyclic graph G*. The key idea is to transform G0 to a directed flow-graph with source s and sink t by a known technique and, after finding a maximum flow, to traverse the graph by a forward-search, which we introduce here
Keywords
directed graphs; field programmable gate arrays; logic design; network topology; FPGA; MCM; directed acyclic graph; directed flow-graph; forward-search; graph extraction; logic circuit; maximal subgraph; min-cut enumeration; s-t minimum cut; size constraints; undirected hypergraph; upper bound; Field programmable gate arrays; Integrated circuit interconnections; Laboratories; Large scale integration; Logic circuits; Partitioning algorithms; Upper bound; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.780123
Filename
780123
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